The present invention relates to a semiconductor device and, more particularly, to an insulated gate bipolar semiconductor device (to be referred to as an IGBT hereinafter) driven by a MOS gate.
As an example of the configuration of an IGBT related to the present invention, FIG. 13 shows the upper surface of a trench IGBT chip, FIG. 14 shows the longitudinal sectional structure of each cell formed in this chip, and FIG. 15 shows the circuit configuration of the chip. A method of fabricating this trench IGBT will be described below.
On the surface of an Nxe2x88x92-type substrate 1 of a P+/N+/Nxe2x88x92-type epitaxial wafer having a P+-type collector layer 6, an N+-type buffer layer 5, and the N+-type substrate 1, a P-type base region 107, a P+-type diffusion region 108, and an N+-type emitter region 9 are formed by impurity diffusion.
Next, trenches are formed through the P-type base region 107 and the N+-type emitter region 9. A gate oxide film 10 is formed on the trench side walls, and polysilicon gate electrodes 11 are buried in these trenches.
On the surface of these polysilicon gate electrodes 11, an interlayer film 12 is formed and patterned to expose the surfaces of the N+-type emitter region 9 and the P+-type diffusion region 108. A collector electrode 13 is formed on the lower surface of the substrate 1, and an emitter electrode 2 is formed on the upper surface. In addition, a gate electrode 3 and a gate line 4 for the whole IGBT are formed. Referring to FIG. 13, a plurality of cells having the structure shown in FIG. 14 are arranged along a plurality of polysilicon gate electrodes 11 positioned below the emitter electrode 2.
Unfortunately, this IGBT related to the present invention has the following problem pertaining to the loss characteristics.
The IGBT loss characteristics include a steady loss and a switching loss, and it is required to reduce these losses.
A general approach is to downsize cells in the IGBT chip to lower the ON voltage (VCE (Sat)), thereby reducing the steady loss.
The switching loss is reduced by lowering a tail loss upon turn-off.
The ON voltage is lowered by downsizing cells by the use of a trench gate structure. On the other hand, the tail loss upon turn-of f is lowered by a method called lifetime control by which crystal defects are increased by irradiation of electron beams to thereby extinguish hole currents within short time periods. The method lowers the tail loss by reducing the carrier concentration, but has an adverse effect in lowing the ON voltage. That is, lowering the ON voltage and lowering the tail loss have a tradeoff relationship as a total loss. So, lowering the tail loss has not been well achieved yet.
Accordingly, it is necessary to lower the switching loss without deteriorating the reduction of the steady loss and the operating characteristics.
A semiconductor device of the present invention is an insulated gate bipolar semiconductor device in which a plurality of cells are formed, and an emitter region of each of the plurality of cells is connected to at least one emitter wire in at least one bonding portion via a common emitter electrode, wherein the threshold value of a cell farther from the bonding portion is larger than that of a cell closer to the bonding portion.
In this semiconductor device, to change the threshold value of a cell in accordance with the distance from the bonding portion to a cell, at least one of the impurity concentration of a base region and the impurity concentration and area of a diffusion region for connecting the base region and the emitter electrode may be changed.
The threshold value of a cell, the impurity concentration of the base region, and the impurity concentration and area of the diffusion region may continuously change in accordance with the distance from the bonding portion.